•	Accelerate product development and reduce time-to-market
•	Cost-efficient and low risk ASIC migration path
•	Real-time signal processing and communications functions
•	Synthesizable VHDL modules can be customized

Nova's IP Cores are modular functions written in the industry standard language of VHDL that are essential components of digital communication and signal processing systems. Fully-tested with proven track records, Nova's IP Cores are available in two formats: VHDL source code or encrypted netlist blocks.

•	Digital IF Receiver
•	Digital Modulator
•	Full Duplex Shaped QPSK Modem

IP Cores can significantly improve system throughput by implementing processing algorithms in FPGAs. The FPGAs act as separate co-processors or pre-processors to increase overall system performance. Many algorithms can be designed to execute in parallel, providing valuable gains in processing throughput. With FPGAs, designers can evaluate and implement design changes in minutes instead of months. In fact, Nova has performed algorithm-to-FPGA-to-ASIC tasks on major commercial programs for a variety of customers such as Texas Instruments and ADC Telecommunications. These devices included high-speed cable modem functions such as digital modulators and demodulators, synchronization, and other related signal processing functions.

Digital IF Receiver

Digital IF Receiver combines a quadrature NCO, a digital mixer and filtering, to translate an IF signal down to baseband. Cascaded Integrator Comb (CIC) filters, and FIR filters provide bandlimiting, decimation, and interpolation to accommodate a variety of signal bandwidths. The Digital IF Receiver is designed to accommodate 12-bit complex data, and includes a total of six, 4th order CIC filters, two 64-tap programmable coefficient FIR filters, a quadrature NCO and two digital mixers.
For more information, please see our Digital Receiver Data Sheet.

Digital Modulator

The Digital Modulator contains a parameterized complex multiplier/mixer and quadrature output NCO. The NCO is a look-up table (LUT) that has a quadrature output, phase accumulator, and phase offset input port. The complex multiplier/mixer multiplies two user-defined inputs with the NCO outputs for amplitude modulation or frequency down conversion.
For more information, please see our Digital Modulator Data Sheet.

Full Duplex Shaped QPSK Modem

The Shaped QPSK modem is designed to provide full duplex communications, with superior spectral containment. The design is compliant with SCA v2.0, with the ability to hold state information between bursts of information, and therefore integrates easily into a SDR (Software Defined Radio) framework. The VHDL design is constructed to perform Shaped QPSK modulation/demodulation with emphasis to support data rates of 64 kbps and 128 kbps in a PLD.
For more information, please see our SQPSK Modem Data Sheet.